Babak falsafi wiki

Electronic design automation software

Verilator is a software programming tool which converts the hardware description languageVerilog to a cycle-accurate behavioral model in the programming languagesC++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free electronic design automation (EDA) software. It is free and open-source software released under a GNU Lesser General Public License (LGPL) only, or an Artistic License

Use

Verilator has seen its widest adoption in the academic and open-source software communities. The semiconductor industry has been more cautious in its adoption of an open-source tool, and has the financial means to use commercial alternatives.

Academic

Researchers have used Verilator to develop new co-simulation environments, as part of general ASIC and FPGA design flows and in performance and power analysis. Verilator is also a popular tool for student dissertations, for example.

Open-source

Verilator is an open-source tool, and has in turn been adopted by a number of other projects. The Fedora Electronic Lab has adopted Verilator as part of its open source design flow for Fedora The OpenRISC architecture from OpenCores includes a cycle accurate reference model, generated from Verilog using Verilator. A paper described how the regression test suite for GCC could be run against a Verilator model of the OpenRISC as a way of detecting errors in the Verilog RTL implementation. TestDrive Profiling Master tool provides the virtual FPGA environment using Verilator.

Commercial

Commercially, Philips

Babak Falsafi is a Swiss computer scientist specializing in computer architecture and digital platform design. He is the founding director of EcoCloud at EPFL, an industrial/academic consortium investigating efficient and intelligent data-centric technologies. He is a professor in the School of Computer and Communication Sciences at EPFL. Prior to that he was a professor of electrical and computer engineering at Carnegie Mellon University, and an assistant professor of electrical and computer engineering at Purdue University. He holds a bachelor's degree in computer science, a bachelor's degree in electrical and computer engineering (both summa cum laude) with distinctions from SUNY Buffalo, and a master's degree and PhD in computer science from University Wisconsin - Madison.

He has made numerous contributions to computer system design and evaluation including a server architecture which laid the foundation for Sun Microsystems' NUMA machines, technologies to minimize (leakage) power in the memory system in the absence of activity (Supply Gating) and in shared memory (Snoop Filtering) prevalent in modern CPUs and multi-socket servers, and memory system accelerators in modern (ARM) CPUs in mobile platforms. He has shown that hardware memory consistency models are neither necessary (in the 90's) nor sufficient (a decade later) to achieve high performance in multiprocessor systems. These results eventually led to fence speculation in modern (x86) CPUs. He argued and demonstrated that the slowdown in silicon efficiency (Dennard's Law) and density scaling (Moore's Law) would lead to Dark Silicon and specialization in servers. These results led to a follow-on study on careful characterization of scale-out workloads on server platforms which laid the foundation for the first generation of Cavium ARM server CPUs, ThunderX.

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